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| (R) X40420, X40421 4kbit EEPROM Data Sheet March 28, 2005 FN8117.0 PRELIMINARY Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch FEATURES * Dual voltage detection and reset assertion --Three standard reset threshold settings (4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V) --VTRIP2 Programmable down to 0.9V --Adjust low voltage reset threshold voltages using special programming sequence --Reset signal valid to VCC = 1V --Monitor two voltages or detect power fail * Battery Switch Backup * VOUT: 5mA to 50mA from VCC; or 250A from VBATT * Fault detection register * Selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) * Selectable watchdog timer interval (25ms, 200ms, 1.4s, off) * Debounced manual reset input * Low power CMOS --25A typical standby current, watchdog on --6A typical standby current, watchdog off --1A typical battery current in backup mode * 4Kbits of EEPROM --16 byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * Built-in inadvertent write protection --Power-up/power-down protection circuitry --Block lock protect 0 or 1/2, of EEPROM * 400kHz 2-wire interface * 2.7V to 5.5V power supply operation * Available packages --14-lead SOIC, TSSOP * *Monitor Voltages: 5V to 1.6V BLOCK DIAGRAM * Memory Security * Battery Switch Backup * VOUT 5mA to 50mA APPLICATIONS * Communications Equipment --Routers, Hubs, Switches --Disk arrays * Industrial Systems --Process Control --Intelligent Instrumentation * Computer Systems --Desktop Computers --Network Servers X40420/21 Standard VTRIP1 Level 4.6V (+/-1%) 4.6V (+/-1%) 2.9V(+/-1.7%) Standard VTRIP2 Level 2.9V(+/-1.7%) 2.6V (+/-2%) 1.6V (+/-3%) Suffix -A -B -C See "Ordering Information" for more details For Custom Settings, call Intersil. DESCRIPTION The X40420/21 combines power-on reset control, watchdog timer, supply voltage supervision, and secondary supervision, manual reset, and Block LockTM protect serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. VOUT V2MON + V2 Monitor Logic VTRIP2 V2FAIL - SDA WP Data Register Command Decode Test & Control Logic Fault Detection Register Status Register EEPROM Array Watchdog and Reset Logic VOUT WDO MR RESET X40420 SCL VOUT VCC (V1MON) BATT-ON VOUT VBATT System Battery Switch + VCC Monitor Logic VTRIP1 - Power-on, Manual Reset Low Voltage Reset Generation RESET X40421 LOWLINE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X40420, X40421 Low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VTRIP1 point. RESET/RESET is active until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Intersil's unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. A battery switch circuit compares VCC with VBATT input and connects VOUT to whichever is higher. This provides voltage to external SRAM or other circuits in the event of main power failure. The X40420/21 can drive 50mA from VCC to 250A from VBATT. The device only switches to VBATT when VCC drops below the low VCC voltage threshold and VBATT. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. PIN CONFIGURATION X40420 14-Pin SOIC, TSSOP V2FAIL V2MON LOWLINE WDO MR RESET VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC BATT-ON VOUT VBATT WP SCL SDA V2FAIL V2MON LOWLINE WDO MR RESET VSS X40421 14-Pin SOIC, TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC BATT-ON VOUT VBATT WP SCL SDA Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with Intersil's Block Lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing operation on a two-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Example Application Unreg. Supply 5V REG BATT-ON VCC VBATT + X40420/21 V2MON V2FAIL VDO RESET MR SCL SDA VOUT Enable SRAM Addr Addr uC NMI VCC IRQ RESET Manual Reset I2C PIN DESCRIPTION Pin 1 2 Name V2FAIL V2MON Function V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. Early Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1. When VCC > VTRIP1, this pin is pulled high with the use of an external pull up resistor. WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog timer goes active. Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up resistor. 3 4 5 LOWLINE WDO MR 2 March 28, 2005 X40420, X40421 PIN DESCRIPTION (Continued) Pin 6 Name RESET/ RESET Function RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. Serial Clock. The Serial Clock controls the serial bus timing for data input and output. Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull down resistor. (>10M typical) Battery Supply Voltage. This input provides a backup supply in the event of a failure of the primary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain the contents of SRAM and also powers the internal logic to "stay awake." If the battery is not used, connect VBATT to ground. Output Voltage. (V) VOUT = VCC if VCC > VTRIP1. IF VCC < VTRIP1 then VOUT = VCC if VCC > VBATT + 0.03V else VOUT = VBATT (ie if VCC < VBATT - 0.03V) Note: There is hysteresis around VBATT 0.03V point to avoid oscillation at or near the switchover voltage. A capacitance of 0.1F must be connected to VOUT to ensure stability. Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current requirements are greater than 50mA. The purpose of this output is to drive an external transistor to get higher operating currents when the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT pin and the external transistor is turned off. In this "backup condition," the battery only needs to supply enough voltage and current to keep SRAM devices from losing their data-there is no communication at this time. 7 8 VSS SDA 9 10 11 SCL WP VBATT 12 VOUT 13 BATT-ON 14 VCC Supply Voltage 3 March 28, 2005 X40420, X40421 PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40420/21 activates a Poweron Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. - It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP1 threshold value for tPURST (selectable) the circuit releases the RESET (X40421) and RESET (X40420) pin allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button X40420/21 System Reset RESET MR Manual Reset X40421 Unreg. Supply 5V Reg 3V Reg VCC RESET V2MON V2FAIL System Reset Low Voltage V2 Monitoring The X40420/21 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum VTRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. The V2FAIL signal remains active until the VCC drops below 1V (VCC falling). It also remains active until V2MON returns and exceeds VTRIP2. V2MON voltage monitor is powered by VOUT. If VCC and VBATT go away, V2MON cannot be monitored. Figure 2. Two Uses of Multiple Voltage Monitoring VOUT X40420 Unreg. Supply R R 5V Reg VCC RESET V2MON V2FAIL System Reset Resistors selected so 3V appears on V2MON when unregulated supply reaches 6V. VOUT Manual Reset By connecting a push-button directly from MR to ground, the designer adds manual system reset capability. The MR pin is LOW while the push-button is closed and RESET/RESET pin remains LOW for tPURST or till the push-button is released and for tPURST thereafter. A weak pull up resistor is connected to the MR pin. Low Voltage V1 Monitoring During operation, the X40420/21 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP1. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The V1FAIL signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP1 for tPURST. Notice: No external components required to monitor two voltages. WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the WDO signal to go active. A minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a Start, Clock Low, Clock High and Stop. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40420/21 control register. 4 March 28, 2005 X40420, X40421 Figure 3. VTRIPX Set/Reset Conditions VTRIPX (X = 1, 2) VCC/V2MON VP WDO SCL 0 7 0 7 0 7 SDA A0h 00h tWC Figure 4. Watchdog Restart .6s SCL SDA Start WDT Reset Stop 1.3s The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. To check if the VTRIPX has been set, set VXMON to a value slightly greater than VTRIPX (that was previously set). Slowly ramp down VXMON and observe when the corresponding outputs (LOWLINE and V2FAIL) switch. The voltage at which this occurs is the VTRIPX (actual). CASE A Now if the desired VTRIPX is greater than the VTRIPX (actual), then add the difference between VTRIPX (desired) - VTRIPX (actual) to the original VTRIPX desired. This is your new VTRIPX that should be applied to VXMON and the whole sequence should be repeated again (see Figure 5). CASE B Now if the VTRIPX (actual), is higher than the VTRIPX (desired), perform the reset sequence as described in the next section. The new VTRIPX voltage to be applied to VXMON will now be: VTRIPX (desired) - (VTRIPX (actual) - VTRIPX (desired)). Note: 1. This operation does not corrupt the memory array. 2. Set VCC = 5V, when VTRIP2 is being programmed Setting a Lower VTRIPx Voltage (x = 1, 2) In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be "reset" according to the procedure described below. Once VTRIPx has been "reset", then VTRIPx can be set to the desired voltage using the procedure described in "Setting a Higher VTRIPx Voltage". V1 AND V2 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40420/21 is shipped with standard V1 and V2 threshold (VTRIP1, VTRIP2) voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40420 trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting a VTRIPx Voltage (x = 1, 2) There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to "reset" the VTRIPx voltage before setting the new value. Setting a Higher VTRIPx Voltage (x = 1, 2) To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIPx threshold voltage to the corresponding input pin (Vcc(V1MON) or V2MON). Then, a program-ming voltage (Vp) must be applied to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for VTRIP1, and 09h for VTRIP2, and a 00h Data Byte in order to program VTRIPx. 5 March 28, 2005 X40420, X40421 Resetting the VTRIPx Voltage To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for VTRIP1 and 0Bh for VTRIP2, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. After being reset, the value of VTRIPx becomes a nominal value of 1.7V or lesser. Note: This operation does not corrupt the memory array. System Battery Switch As long as VCC exceeds the low voltage detect threshold VTRIP, VOUT is connected to VCC through a 5 (typical) switch. When the VCC has fallen below V1TRIP, then VCC is applied to VOUT if VCC is or equal to or greater than VBATT - 0.03V. When VCC drops to less than VBATT 0.03V, then VOUT is connected to VBATT through an 80 (typical) switch. VOUT typically supplies the system static RAM voltage, so the switchover circuit operates to protect the contents of the static RAM during a power failure. Typically, when VCC has failed, the SRAMs go into a lower power state and draw much less current than in their active mode. When VCC returns, VOUT switches back to VCC when VCC exceeds VBATT + 0.03V. There is a 60mV hysteresis around this battery switch threshold to prevent oscillations between supplies. While VCC is connected to VOUT the BATT-ON pin is pulled LOW. The signal can drive an external PNP transistor to provide additional current to the external circuits during normal operation. Operation The device is in normal operation with VCC as long as VCC > VTRIP1. It switches to the battery backup mode when VCC goes away. Condition VCC > VTRIP1 VCC > VTRIP1 & VBATT = 0 0 VCC VTRIP1 and VCC < VBATT Mode of Operation Normal Operation Normal Operation without battery backup capability Battery Backup mode; RESET signal is asserted. No communication to the device is allowed. Control Register The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 8. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, and BP. The X40420 will not acknowledge any data bytes written after the first byte is entered. The state of the Control Register can be read at any time by performing a random read at address 01Fh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. 7 6 5 WD0 4 BP 3 0 2 1 0 PUP1 WD1 RWEL WEL PUP0 RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to "1" prior to a write to the Control Register. Figure 5. Sample VTRIP Reset Circuit VP Adjust V2FAIL RESET VTRIP1 Adj. VTRIP2 Adj. 4.7K 1 14 Run SCL SDA 6 13 X40420 2 9 7 8 C 6 March 28, 2005 X40420, X40421 Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2) VTRIPX Programming Vx = VCC, VxMON Note: X = 1, 2 Let: MDE = Maximum Desired Error No Desired VTRIPX< Present Value YES Execute VTRIPX Reset Sequence MDE+ Acceptable Desired Value Error Range MDE- Error = Actual - Desired Set VX = desired VTRIPX New VX applied = Old VX applied + | Error | Execute Set Higher VX Sequence New VX applied = Old VX applied - | Error | Apply VCC and Voltage > Desired VTRIPX to VX NO Decrease VX Execute Reset VTRIPX Sequence Output Switches? YES Error < MDE- Actual VTRIPX Desired VTRIPX | Error | < | MDE | DONE Error > MDE+ WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. 7 March 28, 2005 X40420, X40421 BP: Block Protect Bit (Nonvolatile) The Block Protect Bits BP determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half the array segment. Protected Addresses (Size) None 100h - 1FFh (256 bytes) Memory Array Lock None Upper Half of Memory Array 0 1 PUP1, PUP0: Power-uppower-up Bits (Nonvolatile) The Power-up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power-up times are shown in the following table. PUP1 0 0 1 1 - Write a one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, and st are the BP bits and qr are the power-up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. - A read operation occurring between any of the previous operations will not interrupt the register write operation. - The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Note: 1. tPURST is set to 200ms as factory default. 2. Watchdog timer bits are shipped disabled. Fault Detection Register (FDR) The Fault Detection Register provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile 7 LV1F BP PUP0 0 1 0 1 Power-on Reset Delay (tPURST) 50ms 200ms (default) 400ms 800ms WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. WD1 0 0 1 1 WD0 0 1 0 1 Watchdog Time Out Period 1.4 seconds 200 milliseconds 25 milliseconds disabled (factory default) Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: - Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). - Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). 6 LV2F 5 0 4 WDF 3 MRF 2 0 1 0 0 0 The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this fault detection register. 8 March 28, 2005 X40420, X40421 Figure 7. Valid Data Changes on the SDA Bus SCL SDA Data Stable Data Change Data Stable At power-up, the Fault Detection Register is defaulted to all "0". The system needs to initialize this register to all "1" before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a "1" to a "0" to indicate the failure. At this moment, the system should perform a read to the register and noted the cause of the reset. After reading the register the system should reset the register back to all "1" again. The state of the Fault Detection Register can be read at any time by performing a random read at address 0FFh, using the special preamble. The FDR can be read by performing a random read at 0FFh address of the register at any time. Only one byte of data is read by the register read operation. MRF, Manual Reset Fail Bit (Volatile) The MRF bit will set to "0" when Manual Reset input goes active. WDF, Watchdog Timer Fail Bit (Volatile) The WDF bit will set to "0" when WDO goes active. LV1F, Low VCC Reset Fail Bit (Volatile) The LV1F bit will be set to "0" when VCC (V1MON) falls below VTRIP1. LV2F, Low V2MON Reset Fail Bit (Volatile) The LV2F bit will be set to "0" when V2MON falls below VTRIP2. Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 7. Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 8. Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 8. 9 March 28, 2005 X40420, X40421 Figure 8. Valid Start and Stop Conditions SCL SDA Start Stop Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 9. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not Figure 9. Acknowledge Response From Receiver SCL from Master Data Output from detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 12. A write to a protected block of memory will suppress the acknowledge bit. 1 8 9 Data Output from Receiver Start Acknowledge 10 March 28, 2005 X40420, X40421 Figure 10. Byte Write Sequence Signals from the Master S t a r t S t o p Slave Address Byte Address Data SDA Bus Signals from the Slave 0 A C K A C K A C K Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page. Figure 11. Page Write Operation S t a r t This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. (1 n 16) Slave Address Byte Address Data (1) Data (n) S t o p Signals from the Master SDA Bus Signals from the Slave 101 00 0 A C K A C K A C K A C K Figure 12. Writing 12 bytes to a 16-byte page starting at location 10. 6 Bytes address pointer ends here Addr = 6 6 Bytes address =5 address 10 address n-1 The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 11 for the address, acknowledge, and data transfer sequence. 11 March 28, 2005 X40420, X40421 Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 13. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. Current Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See Figure 14 for the address, acknowledge, and data transfer sequence. Figure 13. Acknowledge Polling Sequence Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) Issue STOP ACK Returned? YES NO High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO YES Continue Normal Read or Write Command Sequence PROCEED It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 15 for the address, acknowledge, and data transfer sequence. 12 March 28, 2005 X40420, X40421 A similar operation called "Set Current Address" where the device will perform this operation if a stop is issued instead of the second start shown in Figure 15. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter "rolls over" to address 0000H and the device continues to output data for each acknowledge received. See Figure 17 for the acknowledge and data transfer sequence. SERIAL DEVICE ADDRESSING Memory Address Map CR, Control Register, CR7: CR0 Address: 1FFhex FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FFhex General Purpose Memory Organization, A8:A0 Address: 00h to 1FFh General Purpose Memory Array Configuration Memory Address A8:A0 000h Lower 256 bytes 0FFh 100h Upper 256 bytes 1FFh Block Protect Option Slave Address Byte Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: - a device type identifier that is always "1010" when accessing the array and "1011" when accessing the control register and fault detection register. - two bits of "0". - one bit that becomes the MSB of the memory address X4. - last bit of the slave command byte is a R/W bit. The R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. See Figure 16. Figure 14. Current Address Read Sequence Signals from the Master S t a r t Slave Address S t o p 1 A C K SDA Bus Signals from the Slave 101 00 Data 13 March 28, 2005 X40420, X40421 Figure 15. Random Address Read Sequence Signals from the Master S t a r t Slave Address Byte Address S t a r t Slave Address S t o p 1 A C K A C K A C K SDA Bus Signals from the Slave 101 00 0 Data Figure 16. X40410/11 Addressing Slave Byte General Purpose Memory Control Register Fault Detection Register 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 A8 R/W 1 R/W 0 R/W Word Address General Purpose Memory A7 A6 A5 A4 A3 A2 A1 Control Register 1 1 1 1 1 1 1 Fault Detection Register 1 1 1 1 1 1 1 A0 1 1 Word Address The word address is either supplied by the master or obtained from an internal counter. Operational Notes The device powers-up in the following state: - The device is in the low power standby state. - The WEL bit is set to `0'. In this state it is not possible to write to the device. - SDA pin is the input mode. - RESET/RESET Signal is active for tPURST. Figure 17. Sequential Read Sequence Signals from the Master Slave Address Data Protection The following circuitry has been included to prevent inadvertent writes: - The WEL bit must be set to allow write operations. - The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. - A three step sequence is required before writing into the Control Register to change Watchdog Timer or Block Lock settings. - The WP pin, when held HIGH, prevents all writes to the array and all the Register. A C K A C K A C K S t o p SDA Bus 1 A C K Signals from the Slave Data (1) Data (2) Data (n-1) Data (n) (n is any integer greater than 1) 14 March 28, 2005 X40420, X40421 ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. 70C +85C Version Chip Supply Voltage -A or -B -C 2.7V to 5.5V 2.7V to 5.5V Monitored Voltages* 2.6 to 5.5V 1.6V to 3.6V *See ordering Info D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol ICC1(1) ICC2(1) ISB1(1)(7) Parameter Active Supply Current (VCC) Read (Excludes IOUT) Active Supply Current (VCC) Write Non Volatile Memory (Excludes IOUT) Standby Current (VCC) AC (WDT off) Min. Typ.(5) Max. 1.5 3.0 Unit mA mA A Test Conditions VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz VIL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz VSDA = VSCL = VCC Others = GND or VCC VOUT = VCC VBATT = 2.8V VOUT = Open IOUT = 5mA (4.5-5.5V) IOUT = 50mA (4.5-5.5V) IOUT = 250A IOL = 3.0mA (4.5-5.5V) IOH = -0.4mA (4.5-5.5V) Power-up Power-down VIL = GND to VCC VSDA = GND to VCC Device is in Standby(2) 6 10 ISB2(2)(7) Standby Current (VCC) DC (WDT on) 25 0.4 30 1 6 A A A V V IBATT1(3)(7) VBATT Current (Excludes IOUT) IBATT2 (7) VBATT Current (Excludes IOUT) (Battery Backup Mode) Output Voltage (VCC > VBATT + 0.03V or VCC > VTRIP1) Output Voltage (VCC < VBATT - 0.03V and VCC < VTRIP1) {Battery Backup} Output (BATT-ON) LOW Voltage Output (BATT-ON) HIGH Voltage Battery Switch Hysteresis (VCC < VTRIP1) Input Leakage Current (SCL, MR, WP) Output Leakage Current (SDA, V2FAIL, WDO, RESET) Input LOW Voltage (SDA, SCL, MR, WP) Input HIGH Voltage (SDA, SCL, MR, WP) -0.5 VOUT-0.8 30 -30 VCC-0.05V VCC-0.5V VBATT-0.2 VOUT1(7) VOUT2(7) VOLB VOHB VBSH ILI ILO VIL(3) VIH(3) (7) 0.4 V V mV 10 10 A A V V VCC x 0.3 VCC + 0.5 VCC x 0.7 15 March 28, 2005 X40420, X40421 D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol VHYS (7) Parameter Schmitt Trigger Input Hysteresis * Fixed input level * VCC related level Output LOW Voltage (SDA, RESET/ RESET, LOWLINE, V2FAIL, WDO) Min. 0.2 .05 x VCC Typ.(5) Max. Unit V V Test Conditions VOL 0.4 V IOL = 3.0mA (2.7-5.5V) IOL = 1.8mA (2.4-3.6V) VCC Supply VTRIP1(6) VCC Reset Trip Point Voltage Range 2.0 4.55 2.85 4.6 2.9 4.75 4.65 2.95 5 V A, B Version C Version S V A Version B Version C Version S tRPDL(7) VTRIP2(6) VTRIP1 to LOWLINE V2MON Reset Trip Point Voltage Range 0.9 2.85 2.55 1.55 2.9 2.6 1.6 Second Supply Monitor 3.5 2.95 2.65 1.65 5 tRPD2(7) VTRIP2 to V2FAIL Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) Negative numbers indicate charging current, positive numbers indicate discharge current. (4) VIL Min. and VIH Max. are for reference only and are not tested. (5) At 25C, VCC = 3V. (6) See ordering information for standard programming levels. For custom programming levels, contact factory. (7) Based on characterization data only. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2) V V = 100mV VREF VxMON C VREF R + - Output tRPDX = 5s worst case 16 March 28, 2005 X40420, X40421 CAPACITANCE Symbol COUT(1) CIN(1) Note: Parameter Output Capacitance (SDA, RESET, RESET/LOWLINE, V2FAIL, WDO) Input Capacitance (SCL, WP) Max. 8 6 Unit pF pF Test Conditions VOUT = 0V VIN = 0V (1) This parameter is not 100% tested. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V 5V VOUT 4.6k V2MON 4.6k SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW May change from HIGH to LOW Don't Care: Changes Allowed OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 2.06k SDA 30pF RESET WDO/LOWLINE V2FAIL 30pF 30pF A.C. TEST CONDITIONS) Input pulse levels Input rise and fall times Input and output timing levels Output load VCC x 0.1 to VCC x 0.9 10ns N/A VCC x 0.5 Standard output load 17 March 28, 2005 X40420, X40421 A.C. CHARACTERISTICS 400kHz Symbol fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF tSU:WP tHD:WP Cb Note: Parameter SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid Time the bus free before start of new transmission Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time Capacitive load for each bus line 20 Min. 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 +.1Cb(1) 0.6 0 Max. 400 0.9 Unit kHz ns s s s s s s ns s s ns 300 300 ns ns s s 20 +.1Cb(1) 400 pF (1) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR tAA SDA OUT tDH tBUF 18 March 28, 2005 X40420, X40421 WP Pin Timing START SCL Clk 1 Slave Address Byte SDA IN tSU:WP WP tHD:WP Clk 9 Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition Start Condition Nonvolatile Write Cycle Timing Symbol tWC(1) Note: Parameter Write Cycle Time Min. Typ.(1) 5 Max. 10 Unit ms (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Power Fail Timings VTRIPX tRPDL VCC or V2MON tR VRVALID tRPDX tRPDL tRPDX tRPDL tRPDX tF LOWLINE or V2FAIL X = 1, 2 19 March 28, 2005 X40420, X40421 RESET/RESET/MR Timings VTRIP1 VCC tPURST tRPD1 tR RESET VRVALID tF tPURST RESET MR tMD LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25C, VCC = 5V) Symbol tRPD1(1) tRPDL tLR(1) tRPD2(1) tPURST Parameters VTRIP1 to RESET/RESET (Power-down only) VTRIP1 to LOWLINE LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL] VTRIP2 to V2FAIL Power-on Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory default) PUP1=1, PUP0=0 PUP1=1, PUP0=1 VCC, V2MON Fall Time VCC, V2MON Rise Time Reset Valid VCC MR to RESET/ RESET delay (activation only) Pulse width Suppression Time for MR Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 WD1=1, WD0=1 (factory default) Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 Watchdog Reset Time Out Delay WD1=1, WD0=0 Watchdog timer restart pulse width Min. Typ. Max. 5 Unit s ns 500 5 50(1) 200 400(1) 800(1) 20 20 1 500 50 1.4(1) 200(1) 25 OFF 100 200 300 s ms ms ms ms mV/s mV/s V ns ns s ms ms ms tF tR VRVALID t MD tin1 tWDO tRST1 tRST2 tRSP Note: 12.5 1 25 37.5 ms s (1) Based on characterization data. 20 March 28, 2005 X40420, X40421 Watchdog Time Out For 2-Wire Interface Start Clockin (0 or 1) tRSP < tWDO SCL Start SDA tRST tWDO tRST WDO Start WDT Restart Minimum Sequence to Reset WDT SCL SDA VTRIPX Set/Reset Conditions (VTRIPX) VCC/V2MON tTSU WDO tVPS VP tTHD tVPH SCL 0 7 0 7 0 7 tVPO SDA A0h Start 00h tWC 01h* sets VTRIP1 09h* sets VTRIP2 03h* resets VTRIP1 0Bh* resets VTRIP2 * all others reserved 21 March 28, 2005 X40420, X40421 VTRIP1, VTRIP2 Programming Specifications: VCC = 2.0-5.5V; Temperature = 25C Parameter tVPS tVPH tTSU tTHD tWC tVPO VP VTRAN1 VTRAN2 Vtv tVPS WDO Program Voltage Hold time VTRIPX Level Setup time VTRIPX Level Hold (stable) time VTRIPX Program Cycle Program Voltage Off time before next cycle Programming Voltage VTRIP1 Set Voltage Range VTRIP2 Set Voltage Range VTRIPX Set Voltage variation after programming (0-75C). WDO Program Voltage Setup time Description WDO Program Voltage Setup time Min. 10 10 10 10 10 1 15 2.0 0.9 -25 10 Max. Unit s s s s ms ms 18 4.75 3.5 +25 V V V mV s VTRIPX programming parameters are periodically sampled and are not 100% tested. 22 March 28, 2005 X40420, X40421 PACKAGING INFORMATION 14-Lead Plastic Small Outline Gullwing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7 0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) 0.050 (1.27) 0.050"T ypical 0.010 (0.25) 0.020 (0.50) X 45 0.050"Typical 0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.030" Typical 14 Places 0.250" FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 23 March 28, 2005 X40420, X40421 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane .031 (.80) .041 (1.05) See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24 March 28, 2005 X40420, X40421 ORDERING INFORMATION Monitored VCC Supplies 2.9-5.5 VTRIP1 Range 4.6V50mV VTRIP2 Range 2.9V50mV Package 14L SOIC 14L TSSOP Operating Temperature Range 0oC - 70oC -40oC - 85oC 0oC - 70oC -40oC - 85oC 0oC 0oC 0oC 70oC 85oC 85oC 70oC 70oC Part Number with RESET X40420S14-A X40420S14I-A X40420V14-A X40420V14I-A X40420S14-B X40420S14I-B X40420V14-B X40420V14I-B X40420S14-C X40420S14I-C X40420V14-C X40420V14I-C Part Number with RESET X40421S14-A X40421S14I-A X40421V14-A X40421V14I-A X40421S14-B X40421S14I-B X40421V14-B X40421V14I-B X40421S14-C X40421S14I-C X40421V14-C X40421V14I-C 2.6-5.5 4.6V50mV 2.6V50mV 14L SOIC 14L TSSOP -40oC -40oC 1.6-3.6 2.9V50mV 1.6V50mV 14L SOIC 14L TSSOP -40oC - 85oC 0oC - 70oC -40oC 85oC PART MARK INFORMATION 14-Lead SOIC 0/1 X4042XX YYWWXX Package - S/V A, B, or C I - Industrial Blank - Commercial WW - Workweek YY - Year All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 March 28, 2005 |
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